1. Technical Field
The present invention relates to a semiconductor apparatus and a semiconductor memory apparatus, and more particularly, to a discharge technology.
2. Related Art
FIG. 1 is a diagram illustrating the conceptual configuration of a conventional semiconductor memory apparatus. The semiconductor memory apparatus of FIG. 1 includes a memory unit 10, a first wordline discharge unit 20, and a second wordline discharge unit 30.
The memory unit 10 is divided into a first memory string 11 and a second memory string 12. The first memory string 11 is connected to an even bit line BL_E, and the second memory string 12 is connected to an odd bit line BL_O. In each memory string, a plurality of memory cells are connected in series. The first memory string 11 will be representatively described below. A total of 64 nonvolatile memory cells MC0_E through MC63_E are connected in series between a first selection transistor MN10 and a second selection transistor MN11. The first selection transistor MN10 is controlled by the voltage level of a first select signal line DSL, and the second selection transistor MN11 is controlled by the voltage level of a second select signal line SSL. Access to the 64 nonvolatile memory cells MC0_E through MC63_E is controlled by the voltage levels of corresponding wordlines WL0 through WL63. Each of the nonvolatile memory cells is composed of a transistor which includes a control gate and a floating gate.
During a programming operation of the semiconductor memory apparatus, one local wordline selected from the plurality of is local wordlines is driven by a wordline programming voltage VPGM, and remaining unselcted local wordlines are driven by a wordline pass voltage VPASS, which has a level lower than the wordline programming voltage VPGM. When the programming operation is completed, all of the plurality of wordlines WL0 through WL63 are discharged.
For illustration purposes, it is assumed that a first wordline WL0 is selected among the plurality of wordlines WL0 through WL63 and is charged with the wordline programming voltage VPGM and that the remaining unselected wordlines WL1 through WL63 are charged with the wordline pass voltage VPASS, as indicated in FIG. 1.
The first wordline discharge unit 20 is configured to discharge a discharge node N1 of the first wordline WL0 selected among the plurality of wordlines WL0 through WL63 in response to a first discharge pulse signal DIS_EN1. Accordingly, during a period in which the first discharge pulse signal DIS_EN1 is activated, the first wordline WL0 is discharged, and its voltage level is lowered.
The second wordline discharge unit 30 is configured to discharge a common discharge node N2 of the remaining unselected wordlines WL1 through WL63 in response to a second discharge pulse signal DIS_EN2. Accordingly, during a period in which the second discharge pulse signal DIS_EN2 is activated, the remaining unselected wordlines WL1 through WL63 are discharged, and their is voltage levels are lowered.
FIG. 2 is a diagram illustrating a wordline discharge operation of the semiconductor memory apparatus shown in FIG. 1. The principal operations of the semiconductor memory apparatus having the above-mentioned configuration will be described below with reference to FIGS. 1 and 2.
During a programming operation, as mentioned above, the selected wordline WL0 is charged with the wordline programming voltage VPGM, and the remaining unselected wordlines WL1 through WL63 are charged with the wordline pass voltage VPASS. When a discharge operation for the entire wordlines WL0 through WL63 is started, the selected wordline WL0 is discharged through the first wordline discharge unit 20, and the remaining unselected wordlines WL1 through WL63 are discharged through the second wordline discharge unit 30.
At this time, while the first wordline discharge unit 20 discharges only one selected wordline WL0, the second wordline discharge unit 30 should discharge the remaining 63 wordlines WL1 through WL63. Therefore, when compared to the first wordline discharge unit 20, the second wordline discharge unit 30 requires a greater discharge time. In general, the greater the number of loadings that the second wordline discharge unit 30 must discharge is, the greater the time it is for the second wordline discharge unit 30 to discharge them.
Moreover, not only during the programming operation but also during the discharge operation, the voltage of the selected wordline WL0 should be lowered while maintaining a level higher than the voltages of the remaining wordlines WL1 through WL63. As the number of memory cells included in a memory string increases, the number of loadings that the second wordline discharge unit 30 should discharge increases. Accordingly, during the discharge operation, there may be an occasion where the voltages VPASS(N2) of the remaining wordlines WL1 through WL63 could become higher than the voltage VPGM(N1) of the first wordline WL0, as shown in FIG. 2. If such an event occurs, the distribution of threshold voltages of the memory cells connected to the wordlines is likely to change, thereby deteriorating stability.